Semiconductor memory devices such as dynamic random access memory (DRAM) devices are widely used in computers and other electronic devices. As the speed of such electronic devices increases, it is important that the speed of accessing data stored in the memory devices also increases or at least does not decrease as the density of the memory devices increases so that the electronic devices do not have to wait for data.
Most modem DRAMs use a well known set of circuits in an array of memory cells to sense a small charge from a chosen memory cell. The charge is amplified to a much larger, full-rail voltage on a pair of digit lines. Such circuity, called sense amplifiers, essentially function as enabled flip-flops. The data access speed in a DRAM can be enhanced by improving the speed of the sense amplifiers.
A well known enhancement of the sense amplifier circuitry is the addition of isolation gates between the digit lines and a N-channel sense amplifier. Such isolation gates resistively separate the N-sense amplifier from the digit line capacitances. As a result, the N-sense amplifier latches data much more quickly. The benefit of isolation gates is more significant for higher density DRAMs, which have longer digit lines, and thus higher digit line capacitances.
The isolation gates are controlled by a control signal which must be accurately timed in relation to other DRAM signals, such as the signal that activates the N-sense amplifier. If the timing of the control signal is inaccurate, the N-sense amplifier may not operate as desired. Therefore, there is a need for a method to control the isolation gates in a manner that is less sensitive to timing inaccuracies.